1. Field of Invention
The present invention relates to a method of manufacturing a flash memory structure. More particularly, the present invention relates to a flash memory structure that utilizes shallow trench isolation (STI) process to form a buried common source.
2. Description of Related Art
Conventional flash memory is a type of erasable programmable read-only memory (EPROM). Many articles have been written about flash memories. In general, the gate of a flash memory includes a polysilicon floating gate, which is used for storing electric charges, and a control gate, which is used for controlling the access of data. Therefore, EPROM normally has two gate terminals with the floating gate located below the control gate. The control gate and the word line are usually connected, and the floating gate is usually in a "floating" state. In other words, the floating gate is not in contact with any other circuits. An outstanding property of flash memory is its ability to perform a fast, block-by-block memory erase instead of the slow, bit-by-bit erase as in conventional EPROMs. Consequently, speed of operation of a flash memory is very fast. Often, the entire memory can be erased within one or two seconds.
FIG. 1 is the top view of a conventional flash memory structure. In FIG. 1, the control gate 10 is used as a word line. The metallic bit line 12 and the control gate 10 run across each other perpendicularly. On each side of the control gate 10, a drain region 14 and a common source 16 are present. There is a contact window 18 above the drain region 14 for coupling electrically with the bit line 12. Furthermore, field oxide layers 13 surround the aforementioned device for insulation.
FIG. 2A is a cross-sectional view along line 2I--2I of FIG. 1 that shows a conventional flash memory structure. FIG. 2B is a cross-sectional view along line 2II--2II of FIG. 1. First, as shown in FIG. 2A, a common source region 16 is formed within a semiconductor substrate 11. Next, as shown in FIG. 2B, the common source region 16 is isolated by field oxide layers 13, and then control gates 10 are formed above the field oxide layers 13. The control gates 10 can be made from, for example, polysilicon. In order to avoid a coupling effect, a minimum distance "a" must be allowed between the control gate 10 and the common source region 16 as shown in FIG. 2B.
In general, this type of flash memory structure has several defects. Firstly, the field oxide insulation structure produces a rounded corner structure 19 in the common source region 16 close to the control gate 10 when viewed from above (as shown in FIG. 1). Secondly, the field oxide layer in this region has a lateral extension known commonly as the bird's beak as shown in FIG. 2B. Therefore, extra space "a" (as shown in FIG. 1 ) between the control gate 10 and the common source region 16 must be set aside to prevent an unwanted coupling effect.
Normally, most integrated circuits must have some form of insulation for isolating one device from its close neighbors. Field oxide layers used to be one of the most commonly used isolating structure. However, the field oxide layer has gradually been replaced by shallow trench isolation (STI) structures. At present, most flash memory structure uses shallow trench isolation. This is because STI has better structural properties than conventional field oxide structures, and furthermore can save chip area. Usually, shallow trench isolation is formed by first performing an anisotropic dry etching operation to form a trench in a substrate, and then depositing some oxide material into the trench.
However, when shallow trench isolation is applied to form a flash memory structure, the self-aligned method of fabricating a source terminal is no longer appropriate. Furthermore, if an active region is used to define the common source pattern, misalignment may occur. In addition, the area occupied by each device is still large. Moreover, if the common source region and the gate structure are too close together, and the gate oxide layer is too thin, unwanted coupling may still be produced, ultimately leading to a deterioration of device reliability.
In light of the foregoing, there is a need to improve the flash memory structure and method of manufacture